1. Field of the Invention
The present invention generally relates to a TSV (through-silicon via) structure and the method for forming the TSV structure. In particular, the present invention is directed to a through-silicon via with a double-ring structure in order to reduce the adverse electric coupling effect between the conductive substrate in the wafer and the conductive material in the through-silicon via structure.
2. Description of the Prior Art
The through-silicon via technique is a quite novel semiconductor technique. The through-silicon via technique mainly resides in solving the problem of the electrical interconnection of chips and belongs to a new 3D packing field. The hot through-silicon via technique creates products which better meet the market trends of “light, thin, short and small” by the 3D stacking through the through-silicon via, to provide the micro electronic mechanic system (MEMS), the photoelectronics and electronic elements with packing techniques of wafer-level package.
The through-silicon via technique drills holes in the wafer by etching or by laser then fills the holes with conductive materials, such as copper, polysilicon or tungsten to form vias, i.e. conductive channels connecting inner regions and outer regions. At last, the wafer or the dice is thinned to be stacked or bonded together to be a 3D stack IC. In such a way, the wire bonding procedure may be omitted. Using etching or laser to form conductive vias not only omits the wire bonding but also shrinks the occupied area on the circuit board and the volume for packing.
The inner connection distance of the package by the through-silicon via technique, i.e. the thickness of the thinned wafer or the dice, compared with the conventional stack package of wire bonding type, the 3D stack IC has much shorter inner connection distance, so the 3D stack IC performs better in many ways, such as smaller electrical resistance, faster transmission, first noise and better performance. Especially for the CPU, flash memory and memory card, the advantages of the shorter inner connection distance of the through-silicon via technique are much more outstanding. In addition, the package size of the 3D stack IC equals to the size of the dice, so the through-silicon via technique is more valuable in the portable electronic devices.
For the current process and techniques, the through-silicon via technique may divided into two types, namely the via first or the via last. The via first process further includes two variations, called before CMOS and after CMOS. In the via-first-before-CMOS process, through-silicon holes are formed on the silicon wafer and filled with a conductive material before the formation of the CMOS. Considering the high temperature procedures in the later CMOS process, the selection of the conductive material is basically focused on those which can survive after high temperatures, such as poly silicon, rather than the better copper because copper tends to form pumping and is unable to keep a low electrical resistance after being subject to thermal processes over and over again. To be viewed as a whole, the via-first-before-CMOS process is more compatible with the conventional CMOS process. However, the conductive material must bear high temperatures.
In the via-first-after-CMOS process, the formation of the via and the filling of the conductive metal are done after the completion of the CMOS process. The current choice of the conductive metal is copper, which is much better than poly silicon in conductivity concern. Because the filling of copper may fail and some voids are formed due to the formation of void, tungsten gradually becomes an alternative choice. To be viewed as a whole, the filling of copper is particularly difficult and there is possible contamination of copper because the CMOS is completed, which makes it less compatible with the conventional CMOS process.
On top of them, there is an electric coupling effect between the conductive substrate in the wafer and the conductive material in the through-silicon via structure to adversely affect the performance of the device when the device is in operation since both the core conductive layer in the through-silicon via structure as well as the substrate are electrically conductive. As a result, a novel through-silicon via structure as well as a novel method for making such through-silicon via structure are still needed to reduce or even to eliminate the undesirable electric coupling effect between the conductive substrate in the wafer and the core conductive material in the through-silicon via structure.